After sneaking into a trading halt on Monday arvo, shares of the peculiar little Aussie nano-innovator 4DS Memory (ASX:4DS) has literally exploded out of the gate, showering investors in a nigh 150% improvement.

So just what did the patient semiconductor innovator and developer do on Tuesday to erupt all volcanic-like on Wednesday?

That’s easily answered, if not understood.

Between Perth and facilities located in Silicon Valley, 4DS Memory (ASX: 4DS), has proven to be an earnestly patient Aussie semiconductor innovator and developer.

Its point of difference is probably a previously unhealthy obsession with the idea of creating a non-volatile memory technology.

This has made it a niche pioneer. And the 4DS game is all about Interface Switching ReRAM for next generation gigabyte storage in mobile and cloud.

We’ll get to that too.

What’s happened today is management’s come out and said the team has successfully performed an analysis of the Fourth Platform Lot with results that are “significantly better” than 4DS, its board, management, investors – and apparently anyone else – were expecting.

Without explaining any of the tech or background just yet, have a look at what the 4DS interim executive chairman David McAuliffe said this morning, and it doesn’t smack of hyperbole:

“These megabit array results are a turning point for the Company and will now shape the Board’s strategic planning over the coming months. I would like to congratulate both the 4DS and imec teams on achieving this milestone and thank shareholders for their continued support.”

imec btw, is a top R&D and innovation hub in nano-electronics and digital technologies.

For me, it’s the confident understatement, the broad congrats and (my) understanding that whacking this mole has been on the company’s mind since the back end of last year.

So let’s get this out of the way, and then we’ll put it all in context:

Analysis of the Fourth Platform Lot has verified that 4DS has:

• Successfully incorporated its ReRAM memory cells into the imec megabit array
• Validated that 4DS Interface Switching ReRAM technology is transferable from fab to fab
• Demonstrated a fully functional megabit array with 4DS Interface Switching ReRAM memory cells
• Demonstrated consistent read and write speeds equivalent to DRAM
• Proven endurance in excess of 2 billion cycles at DRAM read and write speed on a megabit array
• Demonstrated persistent memory with variable and tuneable retention

Background on 4DS and a heap of context to make this legible…

First, we go back to August last.

4DS was busy on the same task – which was to somehow resolve an etch residue problem which resulted in the partial failure of what was then called the Second Platform Lot (basically the second batch of wafers processed together). In trying to fix this they went and inadvertently caused another issue with the Third Platform Lot (today’s all about the Fourth.)

“Testing of the memory cells used in the imec megabit memory array showed unexpected problems with scaling the memory cell to small dimensions suitable for Storage Class Memory potential applications,” the company told the ASX with no small amount of indiscernable bitterness.

“These results suggest that the memory stack etch mask modification and further optimisation of the etch process utilising this new mask appears to have created another problem, while having resolved the root cause of the electrical shorting of the memory devices in the Second Platform Lot.”

Got that?

Anyway, the end result for the crew was that until the successfully integrating the ReRam stuff into the megabit array could be resolved, 4DS had to accept more work and a long-term delay before it could again get back to its strategic goal of commercialising the technology and making some waves, money and semiconductors.

That was when, to save some dollars, the then MD Ken Hurley hurled himself on his own sword, leaving the company immediately – he was engaged for the specific purpose of leading the commercialisation effort – and promised to re-engage when 4DS was ready to start making cash.

A few months later, 4DS said that the etch process had induced damage to the crystallinity of the 4DS PCMO layer resulting in the write voltage needed to program the cell exceeding the write voltage that the circuitry of the imec megabit memory array could provide.

So, more bad news: it blew a fuse.

Since earlier wafers had shown successful programming of cells of the same size as present in the megabit memory array, the focus turned to further optimising the etch process to ensure both residue-free etching and no crystalline damage to the 4DS PCMO layer.

Christmas came and went, but then in February 4DS revealed some new optimisation changes which were incorporated into the schedule for manufacturing of the Fourth Platform Lot at imec.

4DS also said that it had achieved cell operation in the megabit memory array of the Third Platform Lot using improved test capabilities. This allowed further exploration of optimised programming conditions with the access transistors and write circuitry of imec’s megabit memory platform.

These results suggested the 4DS Interface Switching ReRAM cells were more likely to be compatible with imec’s megabit memory platform which de-risked the testing of the Fourth Platform Lot.

But was this mere speculation? And by now, was anyone listening…

 

23rd August Fab news: Megabit Array Success

Today is big because the company believes it has now demonstrated the successful transfer of all new process improvements and learning cycles developed at the Stanford Nanofabrication Facility into imec’s megabit array.

These process improvements included modification of the PCMO etch process and the composition of the memory cells, and it validated that the technology optimisation is transferable from fab to fab.

After extensive analysis 4DS has now shown for the first time a fully functioning megabit array with 60nm memory cells, access transistors and write circuitry.

Within the fully functioning megabit array 4DS now confirms these terrific milestones:

– Read and write speeds at 27 nanoseconds
– Endurance well in excess of 2 billion cycles; and
– Retention is persistent and tuneable

4DS has always said its focus of the analysis of the megabit array has been on read/write speed and endurance and its goal has always been to look to take advantage of the uniqueness of its technology as an area-based ReRAM.

“imec’s megabit arrays have a lower limit of 60nm for a memory cell but 4DS testing has demonstrated that our ReRAM scales consistently across available cell geometries on megabit arrays.

“The read/write speed and endurance parameters are critical to the Company’s goals in the memory space requiring DRAM-like performance characteristics. 4DS’ ReRAM performance profile to suitably meet this goal has been clearly demonstrated on the Fourth Platform Lot.”

Chief technology officer Ting Yen, on today’s breakthrough: 

“These significant and robust results validate 4DS’ optimisation strategy and the decision to establish a duplicate of imec’s custom testing hardware and software for the megabit array at the 4DS Fremont facility.”

“We are very pleased with our imec collaboration and their comprehensive engineering support that made this significant achievement possible. We would like to thank imec for keeping a focussed engineering and fab effort throughout the fabrication of this megabit array….”

Over the coming weeks 4DS says additional analysis of the megabit array will continue and a meeting is being scheduled with imec in early October to discuss strategic plans.

The question is, will self-sacrificial MD Hurley be back? You know when Ken walks through the door, 4DS have got all their fabs in a row.

 

Now, if you’d like to know more, let’s go back to computing class…
 

DRAM and NAND

Every device or system that processes data needs storage and system memory for computation.

The memories in these devices or systems can be slapped into three distinct categories:

1. internet-of-things (IoT) memories
2. embedded memories; and
3. high-density high-volume memories

The memory requirements (cost, density, speed, endurance, retention, power consumption etc etc) are pretty different for each of these three segments:

• IoT memories tend to be inexpensive, power-efficient, and low-density.

• Memories embedded in complex system chips tend to be fast, area-efficient, and medium-density.

• High-density, high-volume memories must be scalable to small geometries to be cost effective.

So if we’re talking functional high-yield memory technologies – smarty-phones or lappy-tops – they naturally land in one of these three groups. Commercially, while there may be competition for market share within any segment, memories in different segments tend not to compete for market share.

Examples of such devices or systems are remote controls for audio/video, smart thermostats, video door bells, security cameras, automotive electronics, smart phones, tablets, laptops, personal computers, air traffic systems, robotics, data centres… and so on.

Right now high-density high-volume memory segment is currently dominated by DRAM (a US$50 billion market) and NAND Flash (a US$40 billion market).

DRAM is super-fast, exhibits exceptional endurance, and is therefore best suited for fast system memory. DRAM, however, is expensive and volatile (the data needs to be refreshed every 60 milliseconds) and sacrifices retention to maximise speed and endurance.

In sharp contrast, 4DS says NAND Flash is inexpensive with much higher bit capacity and exceptional retention, and is best suited for low-cost silicon storage.

NAND Flash, however, sacrifices both speed and endurance to maximise retention.

For these reasons, the maximum silicon storage in smartphones has increased 32-fold over the past 10 years, at roughly the same cost to the consumer, while system memory has barely doubled. This illustrates that it is affordable to increase silicon storage in many products, but it is not economical to do the same with system memory.

Being limited to 2D, DRAM will likely remain expensive since silicon area largely defines cost per gigabyte. In contrast, the cost of NAND Flash is expected to decline over time thanks to 3D stacking. The cost gap between DRAM and NAND Flash will likely increase over time.
 

4DS: The Mission Statement

“This vast space between DRAM and NAND Flash is therefore an opportunity for innovation. Much like the availability of inexpensive silicon storage enabled a booming new market of products that could not possibly exist without silicon storage (e.g.; smart phones), so will the emergence of new memory technologies lead to new products that we cannot even imagine today.”

Well, today we have at least a small idea.

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